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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICV_CTLR, Virtual Machine Control Register</h1><p>The GICV_CTLR characteristics are:</p><h2>Purpose</h2>
        <p>Controls the behavior of virtual interrupts.</p>

      
        <p>This register corresponds to the physical CPU interface register <a href="ext-gicc_ctlr.html">GICC_CTLR</a>.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICV_CTLR are <span class="arm-defined-word">RES0</span>.</p>
        <p>This register is available when a GIC implementation supports interrupt virtualization.</p>
      <h2>Attributes</h2>
        <p>GICV_CTLR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="22"><a href="#fieldset_0-31_10">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">EOImode</a></td><td class="lr" colspan="4"><a href="#fieldset_0-8_5">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">CBPR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">FIQEn</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">AckCtl</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">EnableGrp1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">EnableGrp0</a></td></tr></tbody></table><h4 id="fieldset_0-31_10">Bits [31:10]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-9_9">EOImode, bit [9]</h4><div class="field">
      <p>Controls the behavior associated with the <a href="ext-gicv_eoir.html">GICV_EOIR</a>, <a href="ext-gicv_aeoir.html">GICV_AEOIR</a>, and <a href="ext-gicv_dir.html">GICV_DIR</a> registers:</p>
    <table class="valuetable"><tr><th>EOImode</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>Writes to <a href="ext-gicv_eoir.html">GICV_EOIR</a> and <a href="ext-gicv_aeoir.html">GICV_AEOIR</a> perform priority drop and deactivate interrupt operations simultaneously. Behavior on a write to <a href="ext-gicv_dir.html">GICV_DIR</a> is unpredictable.</p>
<p>When it has completed processing the interrupt, the virtual machine writes to <a href="ext-gicv_eoir.html">GICV_EOIR</a> or <a href="ext-gicv_aeoir.html">GICV_AEOIR</a> to deactivate the interrupt. The write updates the List registers and causes the virtual CPU interface to signal the interrupt completion to the physical Distributor.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>Writes to <a href="ext-gicv_eoir.html">GICV_EOIR</a> and <a href="ext-gicv_aeoir.html">GICV_AEOIR</a> perform priority drop operation only. Writes to <a href="ext-gicv_dir.html">GICV_DIR</a> perform deactivate interrupt operation only.</p>
<p>When it has completed processing the interrupt, the virtual machine writes to <a href="ext-gicv_dir.html">GICV_DIR</a> to deactivate the interrupt. The write updates the List registers and causes the virtual CPU interface to signal the interrupt completion to the Distributor.</p></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_5">Bits [8:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4">CBPR, bit [4]</h4><div class="field">
      <p>Controls whether <a href="ext-gicv_bpr.html">GICV_BPR</a> affects both Group 0 and Group 1 interrupts:</p>
    <table class="valuetable"><tr><th>CBPR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-gicv_bpr.html">GICV_BPR</a> affects Group 0 virtual interrupts only. <a href="ext-gicv_abpr.html">GICV_ABPR</a> affects Group 1 virtual interrupts only.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-gicv_bpr.html">GICV_BPR</a> affects both Group 0 and Group 1 virtual interrupts.</p>
        </td></tr></table>
      <p>For more information, see <span class="xref">'Priority grouping' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-3_3">FIQEn, bit [3]</h4><div class="field">
      <p>FIQ Enable. Controls whether Group 0 virtual interrupts are presented as virtual FIQs:</p>
    <table class="valuetable"><tr><th>FIQEn</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Group 0 virtual interrupts are presented as virtual IRQs.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Group 0 virtual interrupts are presented as virtual FIQs.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-2_2">AckCtl, bit [2]</h4><div class="field"><p>Arm deprecates use of this bit. Arm strongly recommends that software is written to operate with this bit always cleared to 0.</p>
<p>Acknowledge control.  When the highest priority interrupt is Group 1, determines whether <a href="ext-gicv_iar.html">GICV_IAR</a> causes the CPU interface to acknowledge the interrupt or returns the spurious identifier 1022, and whether <a href="ext-gicv_hppir.html">GICV_HPPIR</a> returns the interrupt ID or the special identifier 1022.</p><table class="valuetable"><tr><th>AckCtl</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>If the highest priority pending interrupt is Group 1, a read of <a href="ext-gicv_iar.html">GICV_IAR</a> or <a href="ext-gicv_hppir.html">GICV_HPPIR</a> returns an interrupt ID of 1022.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>If the highest priority pending interrupt is Group 1, a read of <a href="ext-gicv_iar.html">GICV_IAR</a> or <a href="ext-gicv_hppir.html">GICV_HPPIR</a> returns the interrupt ID of the corresponding interrupt.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-1_1">EnableGrp1, bit [1]</h4><div class="field">
      <p>Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine:</p>
    <table class="valuetable"><tr><th>EnableGrp1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Signaling of Group 1 interrupts is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Signaling of Group 1 interrupts is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-0_0">EnableGrp0, bit [0]</h4><div class="field">
      <p>Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine:</p>
    <table class="valuetable"><tr><th>EnableGrp0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Signaling of Group 0 interrupts is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Signaling of Group 0 interrupts is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing GICV_CTLR</h2>
        <p>This register is used only when System register access is not enabled. When System register access is enabled:</p>

      
        <ul>
<li>For AArch32 implementations, <a href="AArch32-icc_ctlr.html">ICC_CTLR</a> provides equivalent functionality.
</li><li>For AArch64 implementations, <a href="AArch64-icc_ctlr_el1.html">ICC_CTLR_EL1</a> provides equivalent functionality.
</li></ul>
      <h4>GICV_CTLR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Virtual CPU interface</td><td><span class="hexnumber">0x0000</span></td><td>GICV_CTLR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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